CPU Fetch–Decode–Execute Lab

Step through three short programs and watch the PC, MAR, MDR, CIR, accumulator, ALU, buses and memory change on every micro-operation.

Model presets

Reviewed starting states

Add 12 + 7 and store · step 0 of 20

Processor ready

The program counter points to the first instruction.

Active transfer

No transfer

1MAR ← PC
2MDR ← memory[MAR]; PC ← PC + 1
3CIR ← MDR
4control unit decodes opcode and operand
5ACC ← memory[operand]
6ACC ← ACC ± memory[operand]
7memory[operand] ← ACC
8stop the processor

Timeline

Step 0 of 20

Current step: 0.00
Final step: 20.0
Instruction index: 0.00
Phase code: 0.00
PC: 0.00
MAR: -1.00
MDR: 0.00
CIR: 0.00
Accumulator: 0.00
Memory[7]: 0.00
Opcode code: -1.00
Program complete: 0.00

Curriculum map

AQA GCSE Computer Science
Computer Systems → CPU components and the fetch–execute cycle
OCR GCSE Computer Science
Systems Architecture → Registers and the fetch–decode–execute cycle
OCR A-Level Computer Science
Processors → Register transfer notation and processor operation

Model boundaries

The teaching CPU uses one three-digit instruction format: the hundreds digit is an opcode and the final two digits are an address.
Memory has eight displayed locations; addresses 0–3 hold instructions and 5–7 hold data for these reviewed programs.
The model omits cache, pipelining, interrupts and control-bus timing so register transfer remains inspectable.
Arithmetic uses small signed decimal integers; overflow and binary representation are outside this model.

StudyVector-authored simplified stored-program CPU model using standard register-transfer descriptions; mapped to the reviewed curriculum topics shown below.

Accessible text description

A block diagram separates CPU and memory. The CPU contains labelled PC, MAR, MDR, CIR and accumulator registers plus the control unit and ALU. The memory table shows addresses 0 to 7 with encoded instructions or data. The active register and transfer path are highlighted for each reversible step, while a sentence names the bus movement. A register-transfer list highlights one micro-operation at a time. Previous and Next buttons expose the entire fetch, decode and execute sequence without requiring animation or colour perception.